What is RISC? What is RISC V? How are they different?
When talking about processors, x86 and ARM are the two terms that come up the most, especially when talking about recent devices. But there are many other architectures out there. For example, you may have heard the names RISC and RISC-V come up from time to time.
Although they have similar names, they are different concepts. So what is RISC and what is RISC-V? And what is the difference between them? Let's find out with TipsMake through the following article!
What is RISC?
RISC is a broad term that stands for 'Reduced Instruction Set Computer'. Basically, a RISC computer is designed to execute individual, simple instructions. Compared to CISC (Complex Instruction Set Computer), RISC processors use uniform instruction lengths for most of the instructions. In contrast, CISC instructions are more complex and can perform low-level, multi-step operations.
To put it simply, RISC processors can execute simpler, uniform instructions, while CISC can execute instructions of varying complexity and scope. Each RISC instruction can only do one thing at a time, while CISC instructions can do many things at once. Because the instructions are written in code and are simpler in nature, RISC processors often need more instructions to accomplish the same tasks as CISC processors. This difference is compensated for by increasing the speed at which RISC CPUs can execute through the use of pipelining. Because they are simpler, RISC processors can also be designed to be faster than CISC processors, and they can run code more efficiently.
Since RISC is not an architecture but a broad term, many CPU architectures can be considered RISC. One of the most famous RISC processor architectures is ARM, which powers smartphones and more recently some of the laptops and computers we use. Others include PowerPC, which has been used in Apple computers and game consoles for a long time. Meanwhile, x86 can be considered a CISC design because it is more complex.
The term RISC was coined by the Berkeley RISC research project led by David Patterson at the University of California, Berkeley, from 1980 to 1984. As it turned out, the project was actually successful, and the term 'RISC' would go on to encompass all computers with simplified instruction sets – even a competing MIPS project developed by Stanford University around the same time would eventually be referred to as a RISC architecture. For that particular Berkeley project, it would go on to be used by the SPARC microarchitecture developed by Sun Microsystems – an architecture that would eventually serve as the inspiration for the ARM architecture in smartphones.
What is RISC-V?
RISC itself is not a specific architecture, you may have been confused by an architecture that takes and uses the RISC name. That is RISC-V - an instruction set architecture (ISA) developed by the University of California, Berkeley, to embody the principles of RISC processors while also being an open source standard. While ARM, the most well-known RISC architecture, is proprietary and needs to be licensed by chip manufacturers, RISC-V is meant to be royalty-free and, in general, free for everyone to use.
RISC-V began development in 2010 and was released to the open community in 2015. Of course, when RISC-V was released, ARM was already in millions of smartphones around the world. But unlike ARM, RISC-V was developed and released with the goal of releasing a CPU design that was open source, extensible, and deployed on any device without requiring royalties of any kind. According to the designers, having a freely available CPU architecture could significantly reduce the cost of software by allowing for more reuse and allowing for more competition.
RISC-V isn't an architecture that's widely deployed in smartphones or anything like that — after all, most of them use ARM or x86. But it's still in use. More specifically, RISC-V has been used in cloud computing , servers , and embedded applications. Known RISC-V-based designs include the Titan M2 security chip used by the Pixel smartphone. There are many future use cases planned for the RISC-V architecture, including those from big-name companies like NVIDIA and Seagate. Since it's royalty-free, it keeps costs down and makes everyone happy.
How is RISC different from RISC-V?
At first glance, some people might think that RISC-V is a variant of RISC, and RISC is an instruction set architecture. After all, since they have similar names, it is not surprising that there is confusion. As detailed earlier, the difference is that RISC is an actual instruction set architecture, while RISC-V is a general term that covers many CPU architectures.
As mentioned before, RISC is a broad term used to refer to computers with simplified instructions—the term covers a wide range of CPU architectures with simpler designs and capabilities, some of which are actively used by billions of devices and others that have been deprecated over time. And the term exists to distinguish these types of computers from CISC, or complex instruction set computer, a term used to describe the x86 architecture used by most PCs around the world, as well as a handful of other devices.
And then RISC-V is an instruction set architecture based on the RISC design, but compared to other RISC architectures like ARM, RISC-V is open source instead of proprietary, which means that any chip maker can create a design based on RISC-V without having to pay royalties or licensing fees to anyone. It is designed to be used for a wide variety of purposes and is supported by many silicon manufacturers as well as many open source operating systems.
One describes a type of CPU, while the other is a CPU architecture in the true sense of an alternative to ARM and other RISC CPUs.
RISC-V and RISC are not the same
The term RISC is used to refer to certain types of processors and it is a term that defines a range of architectures. However, some people mistakenly believe that RISC is a CPU architecture. These people are probably thinking of RISC-V and confusing it with the term RISC. Now that you know the difference, hopefully you will not confuse the two terms in the future.
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