HomeTech infoQuiz technologyTest of computer architecture P5

Test of computer architecture P5

  1. Question 1. Strip integer representation, n bit in computer is:

    1. 2 (n - 1) -> 2 (n - 1)

    2. 2.n - 1 -> 2.n +1

    3. 2n - 1 -> 2n - 1 - 1
  2. Question 2. For unsigned numbers, the addition on the computer gives false results when:

    1. Add two positive numbers, give negative results

      1. Add two negative numbers, giving positive results

    3. Have to remember out of the highest bit

    4. Both A and B
  3. Question 3. The main task of the ALU is:

    1. Perform addition

      1. As the input of the cumulative register
    3. Change logic or arithmetic of data words
    4. All jobs are told here
  4. Question 4. Most arithmetic and logic operations in microprocessors perform operations between the contents of the device or the contents of the register with:

    1. Accumulated register A fc

    2. PC

    3. Memory address register

    4. Command register

  5. Question 5. The main purpose of the temporary register:
    1. Connect the ALU to the internal data bus of the CPU
    2. Connect the register to the total register
    3. Separate the input and output of ALU
    4. Make sure to save the data of the total register
  6. Question 6. While executing a command, the command register (IR) stores the command:

    1. Before

    2. Now

    3. Later

    4. Always

  7. Sentence 7. The first 640 KB of memory is called:
      1. Memory expansion
    2. Conventional memory
      1. Memory paging

    4. Upper memory

  8. Question 8. For ROM memory, which of the following statements is true:
      1. Can use electricity to delete PROM
      1. PROM is a type of ROM that can be erased and recorded many times
    3. EPROM is a type of ROM that can be erased and recorded many times

      1. Can use electricity to delete EPROM
  9. Question 9. For the SRAM memory chip with a capacity of 16K x 8 bits, the following statement is true:
    1. The address lines are: A0 -> A13
      1. The address lines are: D0 -> D13
      1. The data lines are: A0 -> A14
      1. The data lines are: D1 -> D8
  10. Question 10. Cache L1 Cache and L2 Cache are fabricated by:
      1. SDRAM
    2. SRAM
      1. DRAM
      1. DDRAM
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