Meta's MTIA 300–500 AI Chip Roadmap, Explained

Meta has announced four new generations of its Meta Training and Inference Accelerator (MTIA): MTIA 300, 400, 450, and 500. The custom chips are designed for Meta's own recommendation and generative-AI workloads and are scheduled to enter production or deployment in stages through 2027.

The program can reduce the cost of selected internal workloads and give Meta more control over hardware design. It does not eliminate the company's need for Nvidia, AMD, or other infrastructure suppliers.

What MTIA is designed to do

General-purpose data-center GPUs must support many customers and workloads. Meta can tune MTIA for the models, numerical formats, memory patterns, software frameworks, power limits, and rack designs used inside its own data centers.

The new roadmap emphasizes inference—the work of running trained models to produce recommendations or generated output—while MTIA 300 also targets ranking-and-recommendation training. Inference often depends heavily on memory bandwidth and efficient low-precision computation, so later chips increase those capabilities.

Meta's MTIA custom AI accelerator hardware

The four announced chips

Chip	Primary focus	Announced status or timing
MTIA 300	Training for ranking and recommendation systems	In production
MTIA 400	Broader workloads and an initial step toward generative-AI inference	Testing and preparation for data-center deployment
MTIA 450	Generative-AI inference with substantially higher HBM bandwidth	Targeted for broader deployment in early 2027
MTIA 500	Later inference generation with more bandwidth, memory capacity, and low-precision support	Targeted for the second half of 2027

These dates are company targets, not guarantees. Chip schedules can change because of validation, software readiness, advanced packaging, memory supply, and foundry capacity.

Why memory bandwidth matters

During generative-model inference, the system repeatedly moves model weights and intermediate data between high-bandwidth memory and compute units. In many serving stages, moving that data can be a larger bottleneck than the theoretical arithmetic rate.

Meta says MTIA 450 doubles HBM bandwidth relative to MTIA 400, while MTIA 500 adds further bandwidth and capacity. Comparisons with commercial accelerators require caution: useful performance depends on the full model, batch size, precision, latency target, software stack, power, and cluster configuration.

Broadcom, RISC-V, and TSMC

Meta worked with Broadcom on the chip program, uses the open RISC-V instruction-set architecture in the design, and relies on TSMC for fabrication. “In-house” therefore means Meta directs the architecture for its workloads; it does not mean the company owns the complete design and manufacturing supply chain.

Production also depends on HBM suppliers, advanced packaging, networking, circuit boards, and data-center power. Custom silicon can reduce one form of vendor dependence while creating other supply constraints.

How MTIA fits beside Nvidia and AMD

Meta needs different hardware for large-scale training, recommendation systems, and serving generative models. A custom accelerator is most attractive when a stable internal workload is large enough to justify development and can be mapped efficiently to the chip.

Commercial GPUs remain valuable for frontier-model training, rapidly changing research, third-party software, and workloads that need flexibility. Meta's recent supplier agreements show that MTIA is part of a diversified compute portfolio, not a complete replacement.

What to watch as the roadmap ships

measured throughput and latency on actual Meta models;
performance per watt and total rack cost;
software compatibility and developer effort;
deployment scale rather than sample-chip availability;
yield, HBM, packaging, and foundry constraints;
whether each six-month design step reaches its announced timetable.

The strategic value of MTIA is tighter alignment between Meta's software and its largest repeatable workloads. The real test will be reliable, economical deployment at scale rather than peak specifications alone.